Non-stoichiometric resistive switching memory device and fabrication methods

ABSTRACT

Providing for a resistive switching memory device is described herein. By way of example, the resistive switching memory device can comprise a bottom electrode, a conductive layer, a resistive switching layer, and a top electrode. Further, two or more layers can be selected to mitigate mechanical stress on the device. In various embodiments, the resistive switching layer and conductive layer can be formed of compatible metal nitride or metal oxide materials having different nitride/oxide concentrations and different electrical resistances. Further, similar materials can mitigate mechanical stress on the resistive switching layer and a conductive filament of the resistive switching memory device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/159,135 filed May 19, 2016, which claims the benefit of U.S.Provisional Application Ser. No. 62/165,874, filed May 22, 2015, andentitled “NON-STOICHIOMETRIC RESISTIVE SWITCHING MEMORY DEVICE ANDFABRICATION METHODS”, the entirety of the foregoing applications arehereby expressly incorporated herein by reference and for all purposes.

TECHNICAL FIELD

This disclosure relates generally to electronic memory, for example, thedisclosure describes a resistive switching device configured to have anon-linear current-voltage response.

BACKGROUND

A recent innovation within the field of integrated circuit technology isresistive memory. While much of resistive memory technology is in thedevelopment stage, various technological concepts for resistive memoryhave been demonstrated by the assignee of the present invention and arein one or more stages of verification to prove or disprove associatedtheory(ies). Even so, resistive memory technology promises to holdsubstantial advantages over competing technologies in the semiconductorelectronics industry.

Resistive random access memory (RRAM) is one example of resistivememory. The inventors of the present disclosure believe RRAM has thepotential to be a high density non-volatile information storagetechnology. Generally, RRAM stores information by controllably switchingamong distinct resistive states. A single resistive memory can store asingle bit of information, or multiple bits, and can be configured as aone-time programmable cell, or a programmable and erasable device, asvarious memory models demonstrated by the assignee provide.

Various theories have been proposed by the inventors to explain thephenomenon of resistive switching. In one such theory, resistiveswitching is a result of formation of a conductive structure within anotherwise electrically insulating medium. The conductive structure couldbe formed from ions, atoms that can be ionized under appropriatecircumstances (e.g., a suitable electric field), or other chargecarrying mechanisms. In other such theories, field-assisted diffusion ofatoms can occur in response to a suitable electric potential applied toa resistive memory cell. In still other theories proposed by theinventors, formation of the conductive filament can occur in response tojoule heating and electrochemical processes in binary oxides (e.g., NiO,TiO₂, or the like), or by a redox process for ionic conductors includingoxides, chalcogenides, polymers, and so on.

The inventors expect resistive devices based on an electrode, insulator,electrode model to exhibit good endurance and life cycle. Further, theinventors expect such devices to have high on-chip densities.Accordingly, resistive elements may be viable alternatives tometal-oxide semiconductor (MOS) transistors employed for digitalinformation storage. The inventors of the subject patent application,for instance, believe that models of resistive-switching memory devicesprovide some potential technical advantages over non-volatile Flash MOSdevices.

In light of the above, the inventors endeavor to make furtherimprovements in memory technology, and resistive memory.

SUMMARY

The following presents a simplified summary of the specification inorder to provide a basic understanding of some aspects of thespecification. This summary is not an extensive overview of thespecification. It is intended to neither identify key or criticalelements of the specification nor delineate the scope of any particularembodiments of the specification, or any scope of the claims. Itspurpose is to present some concepts of the specification in a simplifiedform as a prelude to the more detailed description that is presented inthis disclosure.

Various embodiments of the present disclosure provide a resistiveswitching memory device. In some embodiments, the resistive switchingmemory device can comprise a bottom electrode, a conductive layer, aresistive switching layer, and a top electrode. Further, two or morelayers can be selected to mitigate mechanical stress on the device. Invarious embodiments, the resistive switching layer and conductive layercan be formed of compatible metal nitride or metal oxide materialshaving different electrical resistances, and that mitigate mechanicalstress on the resistive switching layer and a conductive filament of theresistive switching memory device.

In a further embodiment, the present disclosure provides a resistiveswitching device. The resistive switching device can comprise a bottomelectrode disposed upon a semiconductor substrate and a resistiveswitching material disposed above the bottom electrode comprising analuminum and nitrogen material: AlNy. Further, the resistive switchingdevice can comprise a conductor material disposed above the resistiveswitching material comprising an aluminum and nitrogen material: AlNx,wherein y>x and a top electrode disposed above the conductor material.

In another embodiment, provided is a resistive switching device. Theresistive switching device can comprise a bottom electrode disposedoverlying a semiconductor substrate and a switching medium overlying thebottom electrode. Further, the switching medium can comprise a resistiveswitching material formed of a metal and nitrogen material: MNy, where yis a positive number. The switching medium can additionally comprise aconductor material in contact with the resistive switching material andcomprising a second metal and nitrogen material: MNx, wherein x is apositive number and y>x. The resistive switching device can additionallycomprise a top electrode disposed above the switching medium.

In a further embodiment, provided is a method for forming asemiconductor device. The method can comprise forming a bottom electrodeoverlying a substrate and forming, in a vacuum sealed environment havinga first nitrogen atmospheric concentration, a first metal nitridematerial. The method can further comprise changing the first nitrogenatmospheric concentration of the vacuum sealed environment to a secondnitrogen atmospheric concentration and forming, in the vacuum sealedenvironment having the second nitrogen atmospheric concentration, asecond metal nitride material having a different percentage of nitrogenthan the first metal nitride material. In addition, the method cancomprise forming a top electrode overlying the second metal nitridematerial.

In additional embodiments, the subject disclosure provides a method forforming a semiconductor device. The method can comprise forming a bottomelectrode upon a semiconductor substrate and forming a resistiveswitching material layer above the bottom electrode comprising analuminum and nitrogen material: AlNy. Further, the method can compriseforming a conductor material above the resistive switching materialcomprising an aluminum and nitrogen material: AlNx, wherein y>x andforming a top electrode above the conductor material.

In still another embodiment, a method is provided for fabricating aresistive switching memory device. The method can comprise disposing asemiconductor substrate within a processing chamber and forming a bottomelectrode overlying the semiconductor substrate. Moreover, the methodcan comprise sealing the processing chamber from an ambient atmosphereand while the processing chamber is sealed from the ambient atmosphere:forming an AlNy material overlying the bottom electrode within acontrolled argon gas and nitrogen gas atmosphere associated with a firstflow rate for nitrogen gas and forming an AlNx material within a secondcontrolled argon gas and nitrogen gas atmosphere associated with asecond flow rate for nitrogen gas, wherein the first flow rate is notequal to the second flow rate. In addition, the method can compriseunsealing the processing chamber from the ambient atmosphere.

The following description and the drawings set forth certainillustrative aspects of the specification. These aspects are indicative,however, of but a few of the various ways in which the principles of thespecification may be employed. Other advantages and novel features ofthe specification will become apparent from the following detaileddescription of the specification when considered in conjunction with thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Various aspects or features of this disclosure are described withreference to the drawings, wherein like reference numerals are used torefer to like elements throughout. In this specification, numerousspecific details are set forth in order to provide a thoroughunderstanding of this disclosure. It should be understood, however, thatcertain aspects of the subject disclosure may be practiced without thesespecific details, or with other methods, components, materials, etc. Inother instances, well-known structures and devices are shown in blockdiagram form to facilitate describing the subject disclosure;

FIG. 1 depicts a block diagram of an example structure providing anon-stoichiometric resistive memory device in various disclosedembodiments;

FIG. 2 illustrates a block diagram of a sample non-stoichiometricresistive switching memory device in alternative disclosed embodiments;

FIG. 3 depicts a block diagram of a sample structure providing anon-stoichiometric resistive memory device in other embodiments;

FIGS. 4-9 illustrate respective block diagrams of an example process forfabricating a disclosed memory device, in some embodiments;

FIG. 10 depicts a block diagram of a sample resistive switching memorydevice according to still other disclosed embodiments;

FIG. 11 illustrates a flowchart of a sample method of fabricating aresistive memory device in further embodiments;

FIG. 12 depicts a flowchart of an example method of fabricating anon-stoichiometric memory device in additional embodiments;

FIG. 13 illustrates a flowchart of a sample method of fabricating anon-stoichiometric memory device according to another embodiment;

FIG. 14 depicts a block diagram of a sample operating and controlenvironment for a memory device according to various disclosedembodiments;

FIG. 15 illustrates a block diagram of an example computing environmentthat can be implemented in conjunction with various embodiments.

DETAILED DESCRIPTION

This disclosure relates to resistive-switching two-terminal memorydevices and one or more process(es) for manufacturing such device(s).Resistive-switching two-terminal memory cells (also referred to asresistive-switching memory cells or resistive-switching memory), asutilized herein, comprise circuit components having two conductivecontacts with an active region between the two conductive contacts. Theactive region of the two-terminal memory device, in the context ofresistive-switching memory, exhibits a plurality of stable orsemi-stable resistive states, each resistive state having a distinctelectrical resistance. Moreover, respective ones of the plurality ofstates can be formed or activated in response to a suitable electricalsignal applied at the two conductive contacts. The suitable electricalsignal can be a voltage value, a current value, a voltage or currentpolarity, or the like, or a suitable combination thereof. Examples of aresistive switching two-terminal memory device, though not exhaustive,can include a resistive random access memory (RRAM), a phase change RAM(PCRAM) and a magnetic RAM (MRAM).

For a non-volatile filamentary-based resistive switching memory cell, aresistive switching layer (RSL) can be selected to have sufficientphysical defect sites therein so as to trap particles in place in theabsence of a suitable external stimulus, mitigating particle mobilityand dispersion. This trapping of conductive particles, in response to asuitable program voltage applied across the memory cell, can cause aconductive path or a filament to form through an inherently electricallyresistive RSL. In particular, upon application of a programming biasvoltage, metallic ions are generated (e.g., from an adjacent activemetal layer or in part within the RSL) that migrate into the RSL layer.More specifically, metallic ions migrate to the voids or defect siteswithin the RSL layer. In some embodiments, upon removal of the biasvoltage, the metallic ions become neutral metal particles and remaintrapped in voids or defects of the RSL layer. When sufficient particlesbecome trapped, a filament is formed and the memory cell switches from arelatively high resistive state, to a relatively low resistive state.More specifically, the trapped metal particles provide the conductivepath or filament through the RSL layer, and the resistance is typicallydetermined by a tunneling resistance through the RSL layer (e.g.,between particles or between the filament and an adjacent conductivelayer).

In some resistive-switching devices, an erase process can be implementedto deform the conductive filament, at least in part, causing the memorycell to return to the high resistive state from the low resistive state.More specifically, upon application of an erase bias voltage, themetallic particles trapped in voids or defects of the RSL become mobileand migrate back towards the active metal layer. This change of state,in the context of memory, can be associated with respective states of abinary bit. For an array of multiple memory cells, a word(s), byte(s),page(s), block(s), etc., resistive states of memory cells can beprogrammed or erased to represent zeroes or ones of binary information,and by retaining those states over time in effect storing the binaryinformation In various embodiments, multi-level information (e.g.,multiple bits) may be stored in such memory cells.

It should be appreciated that various embodiments herein may utilize avariety of memory cell technologies, having different physicalproperties. For instance, different resistive-switching memory celltechnologies can have different discrete programmable resistances,different associated program/erase voltages, as well as otherdifferentiating characteristics. For instance, various embodiments ofthe subject disclosure can employ a bipolar switching device thatexhibits a first switching response (e.g., programming to one of a setof program states) to an electrical signal of a first polarity and asecond switching response (e.g., erasing to an erase state) to theelectrical signal having a second polarity. The bipolar switching deviceis contrasted, for instance, with a unipolar device that exhibits boththe first switching response (e.g., programming) and the secondswitching response (e.g., erasing) in response to electrical signalshaving the same polarity and different magnitudes.

Where no specific memory cell technology or program/erase voltage isspecified for the various aspects and embodiments herein, it is intendedthat such aspects and embodiments incorporate any suitable memory celltechnology and be operated by program/erase voltages appropriate to thattechnology, as would be known by one of ordinary skill in the art ormade known to one of ordinary skill by way of the context providedherein. It should be appreciated further that where substituting adifferent memory cell technology would require circuit modificationsthat would be known to one of ordinary skill in the art, or changes tooperating signal levels that would be known to one of such skill,embodiments comprising the substituted memory cell technology(ies) orsignal level changes are considered within the scope of the subjectdisclosure.

The inventors of the subject application are familiar with additionalnon-volatile, two-terminal memory structures in addition to resistivememory. For example, ferroelectric random access memory (RAM) is oneexample. Some others include magneto-resistive RAM, organic RAM, phasechange RAM and conductive bridging RAM, and so on. Two-terminal memorytechnologies have differing advantages and disadvantages, and trade-offsbetween advantages and disadvantages are common. Thoughresistive-switching memory technology is referred to with many of theembodiments disclosed herein, other two-terminal memory technologies canbe utilized for some of the disclosed embodiments, where suitable to oneof ordinary skill in the art.

Based upon the Inventors extensive experiments, they have come tobelieve that compressive/tensile forces between layers of resistiveswitching devices may have an undesirable effect upon long-term storageperformance of resistive switching devices they have invented.Accordingly, in various embodiments, the inventors desire that thematerials for a resistive switching device, such as a top electrode, aresistive switching material, a conductive material, and a bottomelectrode are somewhat compatible in terms of composition and/orcompressive or tensile stresses. As merely an example, in someembodiments a conductive layer may be a relatively-conductive metalnitride, or the like, and a switching layer may be arelatively-resistive metal nitride (e.g. ceramic), or the like,respectively.

The inventors have conducted controlled fabrication of resistiveswitching devices utilizing a variety of metal nitrides, and havediscovered a combination of materials that enables a working resistiveswitching device expected to have high long term reliability. The useand success of aluminum nitride, as one example, as a resistiveswitching material has been a surprise to the inventors because mostmetal nitrides are highly conductive and are thus unsuitable as aswitching material.

Referring now to the drawings, FIG. 1 illustrates a block diagram of anexample resistive switching memory device 100 according to one or moreembodiments. Resistive switching memory device can comprise a topelectrode 102, a resistive switching layer 104, a conductive layer 106and a bottom electrode 108. In various embodiments, one or more otherlayers can be provided for inter-layer adhesion, conductivity,mitigation of particle diffusion, or the like (e.g., see FIG. 3, infra).

In one or more embodiments, resistive switching memory device 100 caninclude a conductive layer 106 having a composition of AlNx and anadjacent switching layer 104 having a composition of AlNy. Theconductive layer may have a ratio between the metal (e.g. Aluminum) andnitride (MNx) within the range of about 55:45 to about 80:20.Accordingly, in some embodiments, x may be within a range of about 0.80to about 0.25. Further, in various embodiments, the switching layer 104may have a ratio between the metal (e.g. Aluminum) and nitride (MNy)within the range of about 50:50 to about 40:60. Accordingly, in someembodiments, y may be within a range of about 1.00 to about 1.50. As canbe seen, in some embodiments the relationship of y versus x is: y>x. Invarious embodiments, based upon measurements, it is believed that theconductive layer 106 may have an electrical resistance on the order ofabout 1 Kohm to about 100 Kohm, and the resistive switching layer 104may have an initial resistance on the order of 1 Mohms or greater.

In some embodiments, conductive layer 106 and resistive switching layer108 can be formed from the same elements (although as compounds withdifferent proportions). As a result, it is expected that the compressiveor tensile nature of these layers will be similar. In light of this, itis expected that a conductive filament formed within the switchingmaterial layer will be subject to less mechanical stress (e.g.,compressive stress, tensile stress, etc.) in response to repeatedheating and cooling. Accordingly, the reliability of such a resistiveswitching device over many program and erase operations is expected toincrease.

In further embodiments, use of a metal nitride for conductive layer 106can provide conductive material (e.g., particles, atoms, ions, etc.) forfilament formation within resistive switching layer 104. Further themetal nitride can also provide the benefit of a built-in currentcompliance for the resistive switching device (e.g., based on theelectrical resistance of the metal nitride). In some embodiments,switching material for resistive switching layer 104 may be AlNy and theconductive material for conductive layer 106 may be AlNx, y>x, asdiscussed above. In light of the above, it should be understood thatother combinations of switching material and conductive material arewithin embodiments of the present invention. For example metal oxides,e.g. conductive AlOx and switching AlOy, where x<y, may also be used.Other suitable materials known to one of skill in the art, or made knownby way of the context provided herein, are considered within the scopeof the present disclosure.

FIG. 2 illustrates a block diagram of a resistive switching memorydevice 200 according to an alternative embodiment of the presentdisclosure. Resistive switching memory device 200 can comprise a topelectrode 202, conductive layer 204, resistive switching layer 206 andbottom electrode 208. Top electrode 202 and bottom electrode 208 can bemade of suitable conductive materials. Examples of materials for topelectrode 202 or bottom electrode 208 can comprise a metal, a metalalloy, metal nitride or metal oxide, Cu, Al, Ti, W and other suitableconductors. In some embodiments, top electrode 202 or bottom electrode208 can comprise a conductive semiconductor material (e.g., doped Si,doped polysilicon, and so forth). Conductive layer 204 can comprise ametal nitride or metal oxide having a first concentration, x, of nitrideor oxide. Further, resistive switching layer can comprise a metalnitride or metal oxide having a second concentration, y, of nitride oroxide. In various embodiments, y>x.

FIG. 3 illustrates a block diagram of an example memory device 300according to further embodiments of the present disclosure. Memorydevice 300 can comprise multiple layers of aluminum nitride in variousembodiments. In some embodiments, the layers of aluminum nitride canhave disparate concentrations of nitrogen, disparate electricalresistances, or the like, or a suitable combination thereof.

Memory device 300 can comprise a bottom electrode 308 formed of asuitable electrical conductor. Example electrical conductors can includea metal, a metal alloy, a metal-nitride, a metal-oxide, Cu, Al, W or Tior an alloy of the foregoing, a doped semiconductor, another suitableconductor, or a suitable combination of the foregoing. In at least oneembodiment, bottom electrode 308 can be a similar material as conductivelayer 304 or resistive switching layer 306 (e.g., an Al—N material oranother metal nitride MN).

Resistive switching layer 306 is formed of Al—N material. In variousembodiments, resistive switching layer 306 can have a ratio of aluminumto nitrogen within a range from about 50:50 to about 40:60. In someembodiments, the ratio of aluminum to nitrogen can be selected to yieldan inherent electrical resistivity of about 1 mega ohms (Mohms) orgreater (e.g., within a range of about 1 Mohm to about 100 Mohm). TheAl—N material employed for resistive switching layer 306 is referred toas Al—N_(Y) where Y is a positive number selected within a range ofabout 1.00 to about 1.50 in some embodiments. Conductive layer 304 isformed of a second Al—N material, referred to as Al—N_(X), where X is apositive number different from Y. In some embodiments, the Al—N_(X)material can have a ratio of aluminum to nitrogen within a second rangefrom about 55:45 to about 80:20. In one or more embodiments, the secondrange can be selected to yield an inherent electrical resistivity ofabout 1 kilo ohm (Kohm) to about 100 Kohms. X can be a positive numberselected within a range from about 0.25 to about 0.80. In someembodiments, resistive switching layer 306 can have a thickness within arange from about 2 nm to about 20 nm, and conductive layer 304 can havea thickness within a range from about 4 nm to about 100 nm. In one ormore embodiments, resistive switching layer 306 and conductive layer 304can be flipped in orientation (e.g., conductive layer 304 being betweenbottom electrode 308 and resistive switching layer 306, the latter beingbetween conductive layer 304 and top electrode 302).

Further to the above, memory device 300 can comprise a top electrode 302formed of a suitable electrical conductor. Top electrode 302 can includea metal, a metal alloy, a metal-nitride, a metal-oxide, Cu, Al or Ti oran alloy of the foregoing, a doped semiconductor, another suitableconductor, or a suitable combination of the foregoing. In at least oneembodiment, top electrode 302 can be a similar material as conductivelayer 304 or resistive switching layer 306 (e.g., an Al—N material oranother metal nitride MN).

FIGS. 4-9 illustrate block diagrams of an example process method forfabricating a memory device according to one or more embodiments of thepresent disclosure. Referring to FIG. 4, a substrate 400 can beprovided. Substrate 400 can be provided with one or more CMOS devices402 formed therein, or the CMOS devices 402 can be fabricated as part ofprovision of substrate 400. With reference to FIG. 5, one or moreoptional layers 502 can be formed overlying substrate 400. The optionallayers 502 can comprise a front-end layer(s) (e.g. active device layers,passive device layers, etc.), a back-end layer(s) (e.g., dielectriclayers, metal wiring layers, interconnect layers, back-end active devicelayers, and so forth), a conductive layer(s) (e.g., metal, crystallinesilicon, doped semiconductor, metal alloy, metal nitride, metal oxide,and so forth, or a suitable combination thereof), an adhesion layer(s)(e.g., Ti, TiN, Ta, TaN, W, WN, etc.), a diffusion barrier layer(s), anion donor layer(s), or the like, or a suitable combination of theforegoing.

At FIG. 6, there is depicted a block diagram of a bottom electrode 602formed overlying substrate 400 (and optional layer(s) 502, if formed).Bottom electrode 602 can be a suitable electrical conductor, asdescribed herein or as known in the art. FIG. 7 illustrates a metalnitride or metal oxide layer 702 having a first concentration, X, ofnitrogen to metal (also referred to as MN_(X)/MO_(X) layer 702).MN_(X)/MO_(X) layer 702 can be formed in a vacuum sealed chamber with afirst nitrogen/oxygen concentration (e.g., a relatively smallnitrogen/oxygen environment, or a relatively large nitrogen/oxygenenvironment). MN_(X)/MO_(X) layer 702 can be formed with a thickness ofabout 2 nm to about 20 nm, in one or more embodiments.

FIG. 8 depicts a block diagram of a second metal nitride or metal oxidelayer 802 (also referred to as MN_(Y)/MO_(Y) layer 802) overlyingMN_(X)/MO_(X) layer 702. MN_(Y)/MO_(Y) layer 802 can be deposited in thevacuum sealed chamber with a second nitrogen/oxygen concentration, whereY>X. The MN_(Y)/MO_(Y) layer 802 can be formed to a thickness of about 4nm to about 100 nm, in various embodiments. In an embodiment,MN_(Y)/MO_(Y) layer 802 can be formed below MN_(X)/MO_(X) layer 702,rather than the order depicted by FIGS. 7 and 8.

Referring to FIG. 9, there is illustrated a top electrode layer 902formed overlying MN_(Y)/MO_(Y) layer 802. Top electrode 902 can be asuitable electrical conductor, as described herein or as known in theart. Although not depicted, one or more additional optional layers (notdepicted), such as described above at optional layer(s) 502, supra, canbe provided between MN_(Y)/MO_(Y) layer 802 and top electrode layer 902,in various embodiments.

FIG. 10 depicts a block diagram of a sample resistive switching memorydevice 1000 according to additional disclosed embodiments. Resistiveswitching memory device 1000 can comprise a top electrode 1002,resistive switching layer 1006, conductive layer 1008 and bottomelectrode 1012 as described herein. Further, resistive switching memorydevice 1000 can comprise one or more additional layers or sets oflayers. For instance, a first set of layers 1004 can comprise one ormore of: a conductive layer for enhancing electrical conductivitybetween resistive switching layer 1006 and top electrode 1002, anadhesion layer for facilitating good inter-layer adhesion, a barrierlayer for mitigating diffusion of particles (metals such as Cu, Al, O,or the like) between layers, or an ion layer for providing ions toanother layer. In a further embodiment, resistive switching memorydevice can comprise a second set of layers 1010 including one or moreof: a conductive layer, an adhesion layer, a barrier layer or an ionlayer between conductive layer 1008 and bottom electrode layer 1012.

The aforementioned diagrams have been described with respect tointeraction between several components (e.g., layers) of a memory cell,a conductive or resistive switching layer thereof, or a memoryarchitecture comprised of such memory cell. It should be appreciatedthat in some suitable alternative aspects of the subject disclosure,such diagrams can include those components and layers specified therein,some of the specified components/layers, or additionalcomponents/layers. Sub-components can also be implemented aselectrically connected to other sub-components rather than includedwithin a parent component/layer. For example, an intermediary layer(s)can be instituted adjacent to one or more of the disclosed layers. Asone example, a suitable barrier layer that mitigates or controlsunintended oxidation can be positioned between one or more disclosedlayers. In yet other embodiments, a disclosed memory stack or set offilm layers can have fewer layers than depicted. For instance, aswitching layer can electrically contact a conductive wire directly,rather than having an electrode layer there between. Additionally, it isnoted that one or more disclosed processes can be combined into a singleprocess providing aggregate functionality. Components of the disclosedarchitectures can also interact with one or more other components notspecifically described herein but known by those of skill in the art.

In view of the exemplary diagrams described supra, process methods thatcan be implemented in accordance with the disclosed subject matter willbe better appreciated with reference to the flow charts of FIGS. 11-13.While for purposes of simplicity of explanation, the methods of FIGS.11-13 are shown and described as a series of blocks, it is to beunderstood and appreciated that the claimed subject matter is notlimited by the order of the blocks, as some blocks may occur indifferent orders or concurrently with other blocks from what is depictedand described herein. Moreover, not all illustrated blocks arenecessarily required to implement the methods described herein.Additionally, it should be further appreciated that some or all of themethods disclosed throughout this specification are capable of beingstored on an article of manufacture to facilitate transporting andtransferring such methodologies to an electronic device. The termarticle of manufacture, as used, is intended to encompass a computerprogram accessible from any computer-readable device, device inconjunction with a carrier, or storage medium.

FIG. 11 illustrates a flowchart of a sample method 1100 for forming aresistive switching memory device, according to one or more disclosedembodiments. At 1102, method 1100 can comprise forming a bottomelectrode. The bottom electrode can be formed of a suitable conductivematerial, such as a metal, doped semiconductor, or the like. At 1104,method 1100 can comprise depositing (e.g., sputtering) a resistiveswitching layer of a first stress-compatible material of a firstconcentration. The first stress-compatible material can comprise a metalnitride in some embodiments, or a metal oxide in other embodiments. Inan embodiment, the first stress-compatible material can be one partmetal to a range from about 1.00 to about 1.50 parts nitride or oxide.In further embodiments, the resistive switching layer can be formed of athickness within a range of about 2 nanometers (nm) to about 20 nm. At1106, method 1100 can comprise depositing (e.g., sputtering) aconductive layer of a second stress-compatible material of a secondconcentration smaller than the first concentration. In an embodiment,the second stress-compatible material can be the same material as thefirst stress-compatible material. In various embodiments, the secondstress-compatible material can be one part metal to a range from about0.6 to about 0.8 parts nitride or oxide. In at least one embodiment, theconductive layer can be formed of a thickness within a range of about 4nm to about 100 nm.

In various embodiments, for instance when both the conductive layer andthe resistive switching layer are formed from the same materials, withdifferent ratios, both layers may be fabricated in situ. In someembodiments, to form such a device, aluminum may be initially deposited(e.g. sputtered) within an argon and nitrogen-richer environment to formthe resistive switching layer (with a thickness within a range of about2 nm to about 20 nm), then without breaking the vacuum, aluminum may bedeposited (e.g. sputtered) within an argon and nitrogen-poorerenvironment to form the conductive layer (with a thickness within arange of about 4 nm to about 100 nm). In other embodiments, two separatedeposition processes may be used to form the two layers, with or withoutan air break. Materials for the top electrode and bottom electrode mayalso be a conductive nitride, such as a titanium nitride, tantalumnitride, aluminum nitride, or the like.

FIG. 12 illustrates a flowchart of a sample method 1200 according tofurther embodiments of the present disclosure. At 1202, method 1200 cancomprise forming a bottom electrode over a substrate. At 1204, method1200 can comprise depositing metal in a nitrogen or oxygen richenvironment to form a resistive switching layer having high electricalresistance. At 1206, method 1200 can comprise depositing the metal or asecond metal in a nitrogen or oxygen less-rich environment (e.g.,compared to reference number 1204) to form a conductive layer havinglower electrical resistance over the resistive switching layer. At 1208,method 1208 can comprise forming a top electrode over the conductivelayer.

FIG. 13 depicts a flowchart of a sample method 1300 for fabricating aresistive memory device according to one or more additional embodimentsof the present disclosure. At 1302, method 1300 can comprise forming abottom electrode overlying a substrate. The substrate can comprise oneor more CMOS devices, in various embodiments. In such embodiments, thebottom electrode (and other layers, provided below) can be formed withina thermal budget of the CMOS devices.

At 1304, method 1300 can comprise optionally forming one or moreoptional layers selected from a group consisting of: an adhesion layer,a diffusion barrier layer, a conductor layer, and an ion donor layer. Insome embodiments, however, none of these layers can be formed. At 1306,method 1300 can comprise initiating metal deposition in a vacuum sealedand relatively nitrogen rich environment. At 1308, method 1300 cancomprise depositing a first metal nitride layer. The first metal nitridelayer can be formed to a thickness in a range from about 2 nm to about20 nm in some embodiments. At 1310, method 1300 can comprise reducingnitrogen concentration of the relatively nitrogen rich environment to arelatively nitrogen poor environment. At 1312, method 1300 can compriseinitiating a second metal deposition in the reduced nitrogen environmentwithout breaking the vacuum seal. In various embodiments, the secondmetal deposition can comprise a common metal as the first metaldeposition.

At 1314, method 1300 can comprise depositing a second metal nitridelayer. The second metal nitride layer can be overlying and in contactwith the first metal nitride layer. Moreover, the second metal nitridelayer can be formed to have a thickness in a second range from about 4nm to about 100 nm. At 1316, method 1300 can comprise optionally formingone or more second optional layers selected from the group consistingof: an adhesion layer, a diffusion barrier layer, a conductor layer andan ion donor layer. At 1318, method 1300 can comprise forming a topelectrode overlying the second metal nitride layer.

In various embodiments of the subject disclosure, disclosed memory ormemory architectures can be employed as a standalone or integratedembedded memory device with a CPU or microcomputer. Some embodiments canbe implemented, for instance, as part of a computer memory (e.g., randomaccess memory, cache memory, read-only memory, storage memory, or thelike). Other embodiments can be implemented, for instance, as a portablememory device. Examples of suitable portable memory devices can includeremovable memory, such as a secure digital (SD) card, a universal serialbus (USB) memory stick, a compact flash (CF) card, or the like, orsuitable combinations of the foregoing. (See, e.g., FIGS. 14 and 15,infra).

NAND FLASH is employed for compact FLASH devices, USB devices, SD cards,solid state drives (SSDs), and storage class memory, as well as otherform-factors. Although NAND has proven a successful technology infueling the drive to scale down to smaller devices and higher chipdensities over the past decade, as technology scaled down past 25nanometer (nm) memory cell technology, several structural, performance,and reliability problems became evident. A subset of these or similarconsiderations are addressed by the disclosed aspects.

FIG. 14 illustrates a block diagram of an example operating and controlenvironment 1400 for a memory array 1402 of a memory cell arrayaccording to aspects of the subject disclosure. In at least one aspectof the subject disclosure, memory array 1402 can comprise memoryselected from a variety of memory cell technologies. In at least oneembodiment, memory array 1402 can comprise a two-terminal memorytechnology, arranged in a compact two or three dimensional architecture.Example architectures can include a 1T1R memory array, and a 1TnR memoryarray (or 1TNR memory array), as disclosed herein, where n is largerthan 1. Suitable two-terminal memory technologies can includeresistive-switching memory, conductive-bridging memory, phase-changememory, organic memory, magneto-resistive memory, or the like, or asuitable combination of the foregoing.

A column controller 1406 and sense amps 1408 can be formed adjacent tomemory array 1402. Moreover, column controller 1406 can be configured toactivate (or identify for activation) a subset of bit lines of memoryarray 1402. Column controller 1406 can utilize a control signal providedby a reference and control signal generator(s) 1418 to activate, as wellas operate upon, respective ones of the subset of bitlines, applyingsuitable program, erase or read voltages to those bitlines.Non-activated bitlines can be kept at an inhibit voltage (also appliedby reference and control signal generator(s) 1418), to mitigate or avoidbit-disturb effects on these non-activated bitlines.

In addition, operating and control environment 1400 can comprise a rowcontroller 1404. Row controller 1404 can be formed adjacent to andelectrically connected with word lines of memory array 1402. Alsoutilizing control signals of reference and control signal generator(s)1418, row controller 1404 can select particular rows of memory cellswith a suitable selection voltage. Moreover, row controller 1404 canfacilitate program, erase or read operations by applying suitablevoltages at selected word lines.

Sense amps 1408 can read data from, or write data to the activatedmemory cells of memory array 1402, which are selected by column control1406 and row control 1404. Data read out from memory array 1402 can beprovided to an input/output buffer 1412. Likewise, data to be written tomemory array 1402 can be received from the input/output buffer 1412 andwritten to the activated memory cells of memory array 1402.

A clock source(s) 1408 can provide respective clock pulses to facilitatetiming for read, write, and program operations of row controller 1404and column controller 1406. Clock source(s) 1408 can further facilitateselection of word lines or bit lines in response to external or internalcommands received by operating and control environment 1400.Input/output buffer 1412 can comprise a command and address input, aswell as a bidirectional data input and output. Instructions are providedover the command and address input, and the data to be written to memoryarray 1402 as well as data read from memory array 1402 is conveyed onthe bidirectional data input and output, facilitating connection to anexternal host apparatus, such as a computer or other processing device(not depicted, but see e.g., computer 1502 of FIG. 15, infra).

Input/output buffer 1412 can be configured to receive write data,receive an erase instruction, receive a status or maintenanceinstruction, output readout data, output status information, and receiveaddress data and command data, as well as address data for respectiveinstructions. Address data can be transferred to row controller 1404 andcolumn controller 1406 by an address register 1410. In addition, inputdata is transmitted to memory array 1402 via signal input lines betweensense amps 1408 and input/output buffer 1412, and output data isreceived from memory array 1402 via signal output lines from sense amps1408 to input/output buffer 1412. Input data can be received from thehost apparatus, and output data can be delivered to the host apparatusvia the I/O bus.

Commands received from the host apparatus can be provided to a commandinterface 1416. Command interface 1416 can be configured to receiveexternal control signals from the host apparatus, and determine whetherdata input to the input/output buffer 1412 is write data, a command, oran address. Input commands can be transferred to a state machine 1420.

State machine 1420 can be configured to manage programming andreprogramming of memory array 1402 (as well as other memory banks of amulti-bank memory array). Instructions provided to state machine 1420are implemented according to control logic configurations, enablingstate machine to manage read, write, erase, data input, data output, andother functionality associated with memory cell array 1402. In someaspects, state machine 1420 can send and receive acknowledgments andnegative acknowledgments regarding successful receipt or execution ofvarious commands. In further embodiments, state machine 1420 can decodeand implement status-related commands, decode and implementconfiguration commands, and so on.

To implement read, write, erase, input, output, etc., functionality,state machine 1420 can control clock source(s) 1408 or reference andcontrol signal generator(s) 1418. Control of clock source(s) 1408 cancause output pulses configured to facilitate row controller 1404 andcolumn controller 1406 implementing the particular functionality. Outputpulses can be transferred to selected bit lines by column controller1406, for instance, or word lines by row controller 1404, for instance.

In connection with FIG. 15, the systems and processes described belowcan be embodied within hardware, such as a single integrated circuit(IC) chip, multiple ICs, an application specific integrated circuit(ASIC), or the like. Further, the order in which some or all of theprocess blocks appear in each process should not be deemed limiting.Rather, it should be understood that some of the process blocks can beexecuted in a variety of orders, not all of which may be explicitlyillustrated herein.

With reference to FIG. 15, a suitable operating environment 1500 forimplementing various aspects of the claimed subject matter includes acomputer 1502. The computer 1502 includes a processing unit 1504, asystem memory 1506, a codec 1535, and a system bus 1508. The system bus1508 couples system components including, but not limited to, the systemmemory 1506 to the processing unit 1504. The processing unit 1504 can beany of various available processors. Dual microprocessors and othermultiprocessor architectures also can be employed as the processing unit1504.

The system bus 1508 can be any of several types of bus structure(s)including the memory bus or memory controller, a peripheral bus orexternal bus, and/or a local bus using any variety of available busarchitectures including, but not limited to, Industrial StandardArchitecture (ISA), Micro-Channel Architecture (MSA), Extended ISA(EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB),Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus(USB), Advanced Graphics Port (AGP), Personal Computer Memory CardInternational Association bus (PCMCIA), Firewire (IEEE 1394), and SmallComputer Systems Interface (SCSI).

The system memory 1506 includes volatile memory 1510 and non-volatilememory 1514, which can employ one or more of the disclosed memoryarchitectures, in various embodiments. The basic input/output system(BIOS), containing the basic routines to transfer information betweenelements within the computer 1502, such as during start-up, is stored innon-volatile memory 1512. In addition, according to present innovations,codec 1535 may include at least one of an encoder or decoder, whereinthe at least one of an encoder or decoder may consist of hardware,software, or a combination of hardware and software. Although, codec1535 is depicted as a separate component, codec 1535 may be containedwithin non-volatile memory 1512. By way of illustration, and notlimitation, non-volatile memory 1512 can include read only memory (ROM),programmable ROM (PROM), electrically programmable ROM (EPROM),electrically erasable programmable ROM (EEPROM), or Flash memory.Non-volatile memory 1512 can employ one or more of the disclosed memoryarchitectures, in at least some disclosed embodiments. Moreover,non-volatile memory 1512 can be computer memory (e.g., physicallyintegrated with computer 1502 or a mainboard thereof), or removablememory. Examples of suitable removable memory with which disclosedembodiments can be implemented can include a secure digital (SD) card, acompact Flash (CF) card, a universal serial bus (USB) memory stick, orthe like. Volatile memory 1510 includes random access memory (RAM),which acts as external cache memory, and can also employ one or moredisclosed memory architectures in various embodiments. By way ofillustration and not limitation, RAM is available in many forms such asstatic RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), doubledata rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM), and so forth.

Computer 1502 may also include removable/non-removable,volatile/non-volatile computer storage medium. FIG. 15 illustrates, forexample, disk storage 1514. Disk storage 1514 includes, but is notlimited to, devices such as a magnetic disk drive, solid state disk(SSD) floppy disk drive, tape drive, Jaz drive, Zip drive, LS-100 drive,flash memory card, or memory stick. In addition, disk storage 1514 caninclude storage medium separately or in combination with other storagemedium including, but not limited to, an optical disk drive such as acompact disk ROM device (CD-ROM), CD recordable drive (CD-R Drive), CDrewritable drive (CD-RW Drive) or a digital versatile disk ROM drive(DVD-ROM). To facilitate connection of the disk storage 1514 to thesystem bus 1508, a removable or non-removable interface is typicallyused, such as interface 1516. It is appreciated that disk storage 1514can store information related to a user. Such information might bestored at or provided to a server or to an application running on a userdevice. In one embodiment, the user can be notified (e.g., by way ofoutput device(s) 1536) of the types of information that are stored todisk storage 1514 and/or transmitted to the server or application. Theuser can be provided the opportunity to opt-in or opt-out of having suchinformation collected and/or shared with the server or application(e.g., by way of input from input device(s) 1528).

It is to be appreciated that FIG. 15 describes software that acts as anintermediary between users and the basic computer resources described inthe suitable operating environment 1500. Such software includes anoperating system 1518. Operating system 1518, which can be stored ondisk storage 1514, acts to control and allocate resources of thecomputer 1502. Applications 1520 take advantage of the management ofresources by operating system 1518 through program modules 1524, andprogram data 1526, such as the boot/shutdown transaction table and thelike, stored either in system memory 1506 or on disk storage 1514. It isto be appreciated that the claimed subject matter can be implementedwith various operating systems or combinations of operating systems.

A user enters commands or information into the computer 1502 throughinput device(s) 1528. Input devices 1528 include, but are not limitedto, a pointing device such as a mouse, trackball, stylus, touch pad,keyboard, microphone, joystick, game pad, satellite dish, scanner, TVtuner card, digital camera, digital video camera, web camera, and thelike. These and other input devices connect to the processing unit 1504through the system bus 1508 via interface port(s) 1530. Interfaceport(s) 1530 include, for example, a serial port, a parallel port, agame port, and a universal serial bus (USB). Output device(s) 1536 usesome of the same type of ports as input device(s) 1528. Thus, forexample, a USB port may be used to provide input to computer 1502 and tooutput information from computer 1502 to an output device 1536. Outputadapter 1534 is provided to illustrate that there are some outputdevices, such as monitors, speakers, and printers, among other outputdevices, which require special adapters. The output adapter 1534 caninclude, by way of illustration and not limitation, video and soundcards that provide a means of connection between the output device 1536and the system bus 1508. It should be noted that other devices and/orsystems of devices provide both input and output capabilities such asremote computer(s) 1538.

Computer 1502 can operate in a networked environment using logicalconnections to one or more remote computers, such as remote computer(s)1538. The remote computer(s) 1538 can be a personal computer, a server,a router, a network PC, a workstation, a microprocessor based appliance,a peer device, a smart phone, a tablet, or other network node, andtypically includes many of the elements described relative to computer1502. For purposes of brevity, only a memory storage device 1540 isillustrated with remote computer(s) 1538. Remote computer(s) 1538 islogically connected to computer 1502 through a network interface 1542and then connected via communication connection(s) 1544. Networkinterface 1542 encompasses wire and/or wireless communication networkssuch as local-area networks (LAN) and wide-area networks (WAN) andcellular networks. LAN technologies include Fiber Distributed DataInterface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet,Token Ring and the like. WAN technologies include, but are not limitedto, point-to-point links, circuit switching networks such as IntegratedServices Digital Networks (ISDN) and variations thereon, packetswitching networks, and Digital Subscriber Lines (DSL).

Communication connection(s) 1544 refers to the hardware/softwareemployed to connect the network interface 1542 to the system bus 1508.While communication connection 1544 is shown for illustrative clarityinside computer 1502, it can also be external to computer 1502. Thehardware/software necessary for connection to the network interface 1542includes, for exemplary purposes only, internal and externaltechnologies such as, modems including regular telephone grade modems,cable modems and DSL modems, ISDN adapters, and wired and wirelessEthernet cards, hubs, and routers.

The illustrated aspects of the disclosure may also be practiced indistributed computing environments where certain tasks are performed byremote processing devices that are linked through a communicationsnetwork. In a distributed computing environment, program modules orstored information, instructions, or the like can be located in local orremote memory storage devices.

Moreover, it is to be appreciated that various components describedherein can include electrical circuit(s) that can include components andcircuitry elements of suitable value in order to implement theembodiments of the subject disclosure. Furthermore, it can beappreciated that many of the various components can be implemented onone or more IC chips. For example, in one embodiment, a set ofcomponents can be implemented in a single IC chip. In other embodiments,one or more of respective components are fabricated or implemented onseparate IC chips.

As utilized herein, terms “component,” “system,” “architecture” and thelike are intended to refer to a computer or electronic-related entity,either hardware, a combination of hardware and software, software (e.g.,in execution), or firmware. For example, a component can be one or moretransistors, a memory cell, an arrangement of transistors or memorycells, a gate array, a programmable gate array, an application specificintegrated circuit, a controller, a processor, a process running on theprocessor, an object, executable, program or application accessing orinterfacing with semiconductor memory, a computer, or the like, or asuitable combination thereof. The component can include erasableprogramming (e.g., process instructions at least in part stored inerasable memory) or hard programming (e.g., process instructions burnedinto non-erasable memory at manufacture).

By way of illustration, both a process executed from memory and theprocessor can be a component. As another example, an architecture caninclude an arrangement of electronic hardware (e.g., parallel or serialtransistors), processing instructions and a processor, which implementthe processing instructions in a manner suitable to the arrangement ofelectronic hardware. In addition, an architecture can include a singlecomponent (e.g., a transistor, a gate array, . . . ) or an arrangementof components (e.g., a series or parallel arrangement of transistors, agate array connected with program circuitry, power leads, electricalground, input signal lines and output signal lines, and so on). A systemcan include one or more components as well as one or more architectures.One example system can include a switching block architecture comprisingcrossed input/output lines and pass gate transistors, as well as powersource(s), signal generator(s), communication bus(ses), controllers, I/Ointerface, address registers, and so on. It is to be appreciated thatsome overlap in definitions is anticipated, and an architecture or asystem can be a stand-alone component, or a component of anotherarchitecture, system, etc.

In addition to the foregoing, the disclosed subject matter can beimplemented as a method, apparatus, or article of manufacture usingtypical manufacturing, programming or engineering techniques to producehardware, firmware, software, or any suitable combination thereof tocontrol an electronic device to implement the disclosed subject matter.The terms “apparatus” and “article of manufacture” where used herein areintended to encompass an electronic device, a semiconductor device, acomputer, or a computer program accessible from any computer-readabledevice, carrier, or media. Computer-readable media can include hardwaremedia, or software media. In addition, the media can includenon-transitory media, or transport media. In one example, non-transitorymedia can include computer readable hardware media. Specific examples ofcomputer readable hardware media can include but are not limited tomagnetic storage devices (e.g., hard disk, floppy disk, magnetic strips. . . ), optical disks (e.g., compact disk (CD), digital versatile disk(DVD) . . . ), smart cards, and flash memory devices (e.g., card, stick,key drive . . . ). Computer-readable transport media can include carrierwaves, or the like. Of course, those skilled in the art will recognizemany modifications can be made to this configuration without departingfrom the scope or spirit of the disclosed subject matter.

What has been described above includes examples of the subjectinnovation. It is, of course, not possible to describe every conceivablecombination of components or methodologies for purposes of describingthe subject innovation, but one of ordinary skill in the art canrecognize that many further combinations and permutations of the subjectinnovation are possible. Accordingly, the disclosed subject matter isintended to embrace all such alterations, modifications and variationsthat fall within the spirit and scope of the disclosure. Furthermore, tothe extent that a term “includes”, “including”, “has” or “having” andvariants thereof is used in either the detailed description or theclaims, such term is intended to be inclusive in a manner similar to theterm “comprising” as “comprising” is interpreted when employed as atransitional word in a claim.

Moreover, the word “exemplary” is used herein to mean serving as anexample, instance, or illustration. Any aspect or design describedherein as “exemplary” is not necessarily to be construed as preferred oradvantageous over other aspects or designs. Rather, use of the wordexemplary is intended to present concepts in a concrete fashion. As usedin this application, the term “or” is intended to mean an inclusive “or”rather than an exclusive “or”. That is, unless specified otherwise, orclear from context, “X employs A or B” is intended to mean any of thenatural inclusive permutations. That is, if X employs A; X employs B; orX employs both A and B, then “X employs A or B” is satisfied under anyof the foregoing instances. In addition, the articles “a” and “an” asused in this application and the appended claims should generally beconstrued to mean “one or more” unless specified otherwise or clear fromcontext to be directed to a singular form.

Additionally, some portions of the detailed description have beenpresented in terms of algorithms or process operations on data bitswithin electronic memory. These process descriptions or representationsare mechanisms employed by those cognizant in the art to effectivelyconvey the substance of their work to others equally skilled. A processis here, generally, conceived to be a self-consistent sequence of actsleading to a desired result. The acts are those requiring physicalmanipulations of physical quantities. Typically, though not necessarily,these quantities take the form of electrical and/or magnetic signalscapable of being stored, transferred, combined, compared, and/orotherwise manipulated.

It has proven convenient, principally for reasons of common usage, torefer to these signals as bits, values, elements, symbols, characters,terms, numbers, or the like. It should be borne in mind, however, thatall of these and similar terms are to be associated with the appropriatephysical quantities and are merely convenient labels applied to thesequantities. Unless specifically stated otherwise or apparent from theforegoing discussion, it is appreciated that throughout the disclosedsubject matter, discussions utilizing terms such as processing,computing, replicating, mimicking, determining, or transmitting, and thelike, refer to the action and processes of processing systems, and/orsimilar consumer or industrial electronic devices or machines, thatmanipulate or transform data or signals represented as physical(electrical or electronic) quantities within the circuits, registers ormemories of the electronic device(s), into other data or signalssimilarly represented as physical quantities within the machine orcomputer system memories or registers or other such information storage,transmission and/or display devices.

In regard to the various functions performed by the above describedcomponents, architectures, circuits, processes and the like, the terms(including a reference to a “means”) used to describe such componentsare intended to correspond, unless otherwise indicated, to any componentwhich performs the specified function of the described component (e.g.,a functional equivalent), even though not structurally equivalent to thedisclosed structure, which performs the function in the hereinillustrated exemplary aspects of the embodiments. In addition, while aparticular feature may have been disclosed with respect to only one ofseveral implementations, such feature may be combined with one or moreother features of the other implementations as may be desired andadvantageous for any given or particular application. It will also berecognized that the embodiments include a system as well as acomputer-readable medium having computer-executable instructions forperforming the acts and/or events of the various processes.

1-20. (canceled)
 21. A resistive non-volatile memory device, comprising:an electrically conductive bottom electrode formed overlying a substratematerial; an active region formed overlying the bottom electrode, theactive region comprising: a switching layer comprised of a first metaloxide compound (MOy), where y is a relative concentration of oxygen withrespect to atomic metal of the first metal oxide compound; a conductorlayer comprised of one of: a second metal oxide compound (MOx) or ametal nitride compound (MNx), where x is a second relative concentrationof oxygen or nitrogen with respect to atomic metal of the second metaloxide compound or metal nitride compound, where y>x, and wherein theconductor layer is configured to provide metal ions of the atomic metalto form a metal filament within the switching layer in response to avoltage or electric field applied across the resistive non-volatilememory device; and a top electrode overlying the active region.
 22. Theresistive non-volatile memory device of claim 21, wherein the switchinglayer is a non-stoichiometric aluminum oxide compound AlOy.
 23. Theresistive non-volatile memory device of claim 21, wherein the conductorlayer is a non-stoichiometric aluminum oxide compound AlOx or anon-stoichiometric aluminum nitride compound AlNx.
 24. The resistivenon-volatile memory device of claim 21, wherein the first metal oxidecompound is a first non-stoichiometric aluminum oxide compound AlOy andthe conductor layer is a second non-stoichiometric aluminum oxidecompound AlOx or a non-stoichiometric aluminum nitride compound AlNx,where y>x.
 25. The resistive non-volatile memory device of claim 21,wherein the electrically conductive bottom electrode is an electricallyconductive metal oxide or metal nitride material.
 26. The resistivenon-volatile memory device of claim 21, wherein the conductor layer hasa thickness within a range of about 2 nm to about 20 nm.
 27. Theresistive non-volatile memory device of claim 21, wherein the switchinglayer has a thickness within a range of about 4 nm to about 100 nm. 28.The resistive non-volatile memory device of claim 21, wherein theswitching layer has a thickness within a range of about 4 nm to about100 nm and the conductor layer has a thickness within a range of about 2nm to about 20 nm.
 29. The resistive non-volatile memory device of claim21, wherein the conductor layer is in physical contact with theswitching layer, the electrically conductive bottom electrode is inphysical contact with one of: the switching layer or the conductorlayer, and the top electrode is in contact with a second of: theswitching layer or the conductor layer.
 30. The resistive non-volatilememory device of claim 21, wherein: the first metal oxide compound is afirst non-stoichiometric aluminum oxide compound AlOy with a thicknessin a range of about 4 nm to about 100 nm; the conductor material is anon-stoichiometric aluminum nitride compound AlNx, where y>x, with asecond thickness in a second range of about 2 nm to about 20 nm; and atleast one of: the electrically conductive bottom electrode is anelectrically conductive metal oxide compound; or the top electrode is anelectrically conductive metal nitride compound.
 31. A method offabricating a resistive switching memory device, comprising: disposing asemiconductor substrate within a processing chamber; forming a bottomelectrode overlying the semiconductor substrate; forming a layer ofmetal oxide compound overlying the bottom electrode, the metal oxidecompound comprising an atomic metal and atomic oxygen and configured toreceive particles of the atomic metal from exterior to the layer ofmetal oxide compound within the layer of metal oxide compound; forming alayer of metal nitride compound overlying the bottom electrode and incontact with the layer of metal oxide compound, wherein the layer ofmetal nitride compound is configured to provide the particles of theatomic metal to form a conductive structure within the layer of metaloxide compound in response to a voltage or electric field applied to theresistive switching memory device; and a top electrode overlying thelayer of metal oxide compound and the layer of metal nitride compound.32. The method of claim 31, further comprising forming the layer ofmetal oxide compound from about 1.00 to about 1.50 parts oxide.
 33. Themethod of claim 31, further comprising forming the layer of metal oxidecompound with a thickness within a range of about 2 nm to about 20 nm.34. The method of claim 33, further comprising forming the layer ofmetal oxide compound to have a ratio of metal to oxide and the thicknesswithin the range of about 2 nm to about 20 nm to produce an electricalresistance for the layer of metal oxide compound within a range of about1 mega-ohms to about 100 mega-ohms.
 35. The method of claim 31, furthercomprising forming the layer of metal nitride material from one partmetal to a range from about 0.6 to about 0.8 parts nitride.
 36. Themethod of claim 31, further comprising forming the layer of metalnitride compound with a thickness within a range of about 4 nm to about100 nm.
 37. The method of claim 36, further comprising forming the layerof metal nitride compound to have a ratio of metal to nitrogen and thethickness within the range of about 4 nm to about 100 nm to produce anelectrical resistance for the layer of metal nitride compound within arange of about 1 kilo-ohms to about 100 kilo-ohms.
 38. The method ofclaim 31, further comprising: forming the layer of metal oxide compoundfrom one part aluminum and a range from about 1.00 to about 1.50 partsoxide; and forming the layer of metal nitride compound from one partaluminum and a second range from about 0.6 to about 0.8 parts nitride.39. The method of claim 38, further comprising: forming the layer ofmetal oxide compound to have a first thickness within a first range ofabout 2 nm to about 20 nm; and forming the layer of metal nitridecompound to have a second thickness within a second range of about 4 nmto about 100 nm.
 40. The method of claim 39, further comprising formingthe layer of metal oxide compound to be a non-stoichiometric metal oxidecompound.